In current memory systems, data stored in volatile memories (e.g., DRAM) must be periodically refreshed to compensate for inherent leakage of capacitors in memory cells. Conventionally, refreshing includes, for example, sensing data out of each row of memory and subsequently writing the data back to the same respective row. As a result, the original charge level in each memory cell is restored and data preserved.
While many approaches for implementing memory refreshes to compensate for leakage are well known in the art, these approaches have struggled when applied to the increasingly demanding operating speeds and applications of memories today. For example, data stored in rows of memory physically adjacent a repeatedly accessed row may degrade more quickly than data stored in other rows. That is, due to coupling effects, cell to cell leakage may increase, and accessing a row a relatively high number (e.g., 100,000) of times during a particular period of time (e.g., less than 32 ms) may degrade data stored in rows physically adjacent the accessed row. While some approaches have strived to ensure no row suffers from “row hammering” effects by tracking the number of times every row of a memory is accessed, maintaining counts in this manner is cumbersome and requires a relatively large footprint.